The present invention relates to the formation of semiconductor devices. More particularly, the invention relates to the formation of semiconductor devices with pitch reduction using oxide spacers.
The packing density of semiconductor devices may increase twice by about every one and half year. The high packing density increases productivity and device speed and also reduces power consumption. However, as the packing density increases, the cost increase and the yield reduction are also exponentially increasing. Since the largest cause of exponential increase of cost and yield reduction may be related to the lithography technology, alternative methods for patterning a mask have been sought to replace optical lithography. One such technology is the double mask scheme which patterns the mask layer twice to make half pitch. However, the double mask method it is limited by precision of overlaying.
In general, spacer lithography provides a sacrificial layer and then etches the sacrificial layer into sacrificial structures. A conformal chemical vapor deposition (CVD) is then used to form a conformal layer over and around the sacrificial structures. An etchback is used to etch the horizontal layers of the conformal layer. The sacrificial structure is then removed to form spacer or fin structures of the conformal layer. Conventionally, the thickness of the spacer may be 10 nm or less. To provide a desired conformal layer, the conventional CVD deposition may require a high temperature CVD. Such high temperatures may be detrimental to the semiconductor device. The high temperature may cause a process to go beyond a device thermal budget. In addition, if doping has previously been done, the high temperature may be detrimental to the doped areas.
In addition, such CVD processes are limited with regards to the sacrificial layer and spacer. Generally, a sacrificial layer of silicon oxide would provide a spacer of silicon nitride. A sacrificial layer of silicon nitride would provide a sacrificial layer of silicon oxide.